1. Technical Field
The present invention relates generally to the field of semi-conductor manufacturing and, more specifically, to a method for forming sidewall spacers in field effect transistors.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.) One of the bedrock technologies that has allowed FETs to be widely used is the use of gate sidewall spacers. Typical sidewall spacers are formed using a conformal deposition of a spacer material over the gate structure, followed by a directional etch, as disclosed in Pogge, U.S. Pat. No. 4,256,514, "Method for Forming a Narrow Dimensioned Region on a Body," assigned to International Business Machines, Inc. The directional etch removes all the spacer material from the horizontal surfaces, but leaves "spacers" at the sidewalls of the gates. Turning to FIGS. 38 and 39, a prior art sidewall spacer is illustrated. As illustrated in FIG. 38, sidewall spacer material 3804 is conformally deposited over a gate 3802 on a wafer 3800. By directionally etching the sidewall spacer material, sidewall spacers 3902 remain adjacent the gate 3802. These spacers are inherently self-aligned with the gate. By implanting, forming the sidewall spacers, and then implanting again, the areas of the wafer closest to the gate edge can be doped less than the other active regions. Thus, sidewall spacers allow for a lighter doped region to be formed at the gate edge with the width of that region defined by the width of the spacer.
Unfortunately, the sidewall spacers has several limitations. First, sidewall spacer technology has a limited ability to be scaled to smaller dimensions. In particular, the maximum width of a spacer created by this process is the height of the vertical structure it adjoins. Thus, in polysilicon gate applications the thickness of the gate polysilicon cannot scale downwards without also making the sidewall spacers smaller. If the sidewall spacers are made too small, silicide may bridge across the spacer is subsequent processing steps, and thus form unwanted shorts.
Second, the prior art sidewall spacers provide limited ability to selectively dope the gate-source and gate-drain transitions. In particular, the prior art only had the ability to implant across the entire active area (except where blocked by the gate), then form the sidewall spacer, and implant again across the entire active area (except where blocked by the gate and sidewall spacers). Thus, any dopant added to the gate edge also had to be added across the entire active area. This severely limited the type of implants that could be made.
For example, forming an implant across the entire active region to increase the background doping can help prevent punchthru at the device channel, but by implanting across the entire active region it will also undesirably affect the parasitic capacitances of the source and drain regions.
Third, traditional methods of creating a sidewall spacer can create pattern density effects at the gate polysilicon etch which can cause increased across chip linewidth variation. In particular, because the etch methods used today use a low pressure, the etch rate is determined in part by the amount of available reactant species. If there is a region where most everything is being etched, the reactants will be consumed quickly relative to the regions where most of the material is protected by photoresist. This causes across the across chip linewidth variation.
Thus, there was a need for improved method of fabricating field effect transistors and resulting improved FET structures.